A system including an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a DRP (Dynamically Reconfigurable Processor), or the like has been put into practical use. This system has a plurality of circuits (hereinafter, called a function circuit) for realizing a single function under the control of a CPU (Central Processing Unit). This system has a shared memory, as a working memory of the CPU and a plurality of the function circuits. With the use of this system, cost and an occupation area of a memory in a board can be reduced.
In the above-described system, a plurality of the function circuits simultaneously transmit data signals to a bus connected to the shared memory. When a plurality of the function circuits simultaneously transmit the data signals to the bus, the above-described system becomes impossible to discriminate the signals from a plurality of the function circuits. When the system becomes impossible to discriminate the signals, the system becomes impossible to accurately perform the communication of information. In order to prevent the above-described matters, the system has an arbitrator provided between the shared memory and each of the function circuits. This arbitrator performs arbitration to assign a use right of the bus to each of the function circuits. Specifically, the arbitrator gives a prescribed data transfer time to each of the function circuits at a certain interval, according to a rule of a predetermined priority order and so on, to perform arbitration.
In the above-described arbitrator, setting of the priority order and so on of each of the function circuits is previously performed, in order to perform the arbitration. It is necessary that the setting of the arbitrator is performed in consideration of required specifications of each standard bus (a bus meeting a prescribed standard such as PCIe) and each of the function circuits. The required specification includes processing bands of the each standard bus and each of the function circuits, for example.
As described above, it is necessary that the setting of the arbitrator is properly performed so that the processing of each of the function circuits is within the required specification. However, in the above-described system, it is difficult that the setting of the arbitrator is properly performed because of the sharing of a memory and the conflict between the function circuits and so on. Furthermore, the above-described system does not have a scheme to confirm whether the set arbitration content of the arbitrator is proper.